Am29F800T

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PRELIMINARY
Am29F800T/Am29F800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS
5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
n
10% for read and write operations
— Minimizes system level power requirements
±
n
Embedded Program Algorithm
— Automatically programs and verifies data at
specified address
n
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
n
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
n
Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
n
Package options
— 44-pin SO
— 48-pin TSOP
n
Erase Suspend/Resume
— Supports reading data from or programming
data to a sector not being erased
n
Minimum 100,000 write/erase cycles guaranteed
n
High performance
— 70 ns maximum access time
n
Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
n
Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
n
Enhanced power management for standby
mode
—1
n
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
A typical standby current
n
Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
n
Hardware RESET pin
— Resets internal state machine to the read mode
n
Embedded Erase Algorithm
— Automatically pre-programs and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F800 is an 8 Mbit, 5.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase capability, the 8 Mbits
of data are divided into 19 sectors as follows: one 16
Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte.
Eight bits of data appear on DQ0–DQ7 in byte mode; in
word mode 16 bits appear on DQ0–DQ15. The
Am29F800 is offered in 44-pin SO and 48-pin TSOP
packages. This device is designed to be programmed
in-system with the standard system 5.0 Volt V
CC
sup-
ply. A V
PP
of 12.0 volts is not required for program or
erase operations. The device can also be programmed
in standard EPROM programmers.
The standard Am29F800 offers access times of 70 ns, 90
ns, 120 ns, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminat
e bu
s
contention, t
he d
evice has separate
chip
enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and program circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
8/18/97
Publication#
20375
Rev:
C
Amendment/
+1
Issue Date:
August 1997
5.0 V
m
PRELIMINARY
of the device is similar to reading from 12.0 Volt Flash
or EPROM devices.
The Am29F800 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automat-
ically times the erase pulse widths and verifies proper
cell margin.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations. A low V
CC
detector au-
tomatically inhibits write operations during power tran-
siti
ons.
The
end o
f program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29F800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal sta
te mach
ine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need re-writing after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F800 is erased when
shipped from the factory.
The Am29F800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sec-
tors of memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F800 memory electrically erases all
bits within a sector simultaneously via Fowler-Nor-
dhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM program-
ming mechanism of hot electron injection.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
2
Am29F800T/Am29F800B
8/18/97
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part No:
Am29F800
Ordering Part No: V
CC
= 5.0 V
±
10%
-70
-90
-120
-150
Max Access Time (ns)
70
90
120
150
CE (E) Access (ns)
70
90
120
150
OE (G) Access (ns)
30
35
50
55
BLOCK DIAGRAM
DQ0–DQ15
V
CC
V
SS
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
BYTE
RESET
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE
OE
STB
STB
Y-Decoder
Y-Gating
V
CC
Detector
Timer
X-Decoder
Cell Matrix
A0–A18
A–1
20375C-1
8/18/97
Am29F800T/Am29F800B
3
PRELIMINARY
CONNECTION DIAGRAMS
SO
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
20375C-2
4
Am29F800T/Am29F800B
8/18/97
PRELIMINARY
CONNECTION DIAGRAMS
A15
1
48
A16
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
2
3
4
5
6
7
8
47
46
45
44
43
42
41
40
39
38
37
36
35
34
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
9
10
11
12
13
14
15
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
A18
16
33
DQ2
A17
A7
A6
A5
A4
A3
A2
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
DQ9
DQ1
DQ8
DQ
0
OE
V
SS
CE
A0
A1
25
Standard TSOP
20375C-3
A16
1
48
A15
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
9
10
11
12
13
14
15
47
46
45
44
43
42
41
40
39
38
37
36
35
34
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
DQ2
16
33
A18
DQ9
DQ1
DQ8
D
Q0
OE
V
SS
CE
A0
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
A17
A7
A6
A5
A4
A3
A2
25
A1
Reverse TSOP
20375C-4
8/18/97
Am29F800T/Am29F800B
5
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
2
3
4
5
6
7
8
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